The present invention relates to a process for manufacturing semiconductor wafers. More particularly, the present invention relates to a semiconductor manufacturing process which produces extremely flat, double side polished semiconductor wafers having an enhanced gettering layer on the back surface of the semiconductor wafer.
The semiconductor industry continues to design integrated circuit devices which utilize increasingly smaller and more complex geometries. As a result, the semiconductor substrates, such as silicon wafers, used to build devices are subject to increasingly tighter constraints and must have extremely low defect concentrations and be extremely flat to ensure proper device performance. Substrate global flatness is generally characterized by total thickness variation (TTV), which is the difference between the minimum and maximum values of thickness encountered in the wafer. The site flatness on the substrate is generally characterized by Site Total Indicated Reading (STIR), which is the distance between the highest and lowest points on a site from a specified reference plane.
Conventional techniques such as the so-called Czochralski process are well known in the art for growing single crystal ingots used to produce semiconductor wafers. Once an ingot of a semiconductor material, such as silicon, is grown and shaped, it is generally sliced into individual wafers and refined by etching and/or lapping and grinding to increase flatness. Generally, the substrate edges are rounded and the wafer etched to remove any damage and contamination. Finally, the wafers are polished on one or both sides and cleaned to provide a semiconductor wafer suitable for device fabrication. At various points in the manufacturing process the wafer can be treated such that its gettering capabilities are increased.
When polishing the surfaces of a semiconductor substrate, manufacturers generally use either single sided or double sided polishing equipment. With the increasing flatness requirements for substrates necessitated by more complex geometries, double side polishing is becoming much more important and is being increasingly utilized by semiconductor substrate manufactures as it provides increased substrate flatness as compared to single side polishing.
One limitation of the use of double side polishing, however, is that conventional techniques have not allowed the production of extremely flat, double side polished wafers which have enhanced gettering characteristics on the back surface of the wafer. Enhanced gettering layers have conventionally been created on the back surface of the wafer by damage techniques such as sandblasting, for example, or by growing a thin polysilicon film on the back surface. Wafers having enhanced gettering characteristics may be desirable to some device manufacturers as this type of external gettering can trap and hold many types of impurities and keep them from migrating toward the front surface region of the semiconductor wafer where devices are ultimately printed. Extremely thick polysilicon gettering layers on the back surface are very expensive and time consuming to grow and can cause contamination problems of the front surface. Thinner enhanced gettering layers are much more easily removed by polishing pads as compared to single crystal materials, and hence, conventional double side polishing almost completely removes and destroys thinner enhanced gettering layers during the double side polishing process. As such, a need exists in the semiconductor industry for a semiconductor manufacturing process incorporating double side polishing which produces extremely flat semiconductor substrates yet allows an enhanced gettering layer to remain intact on the back surface of the semiconductor wafer for use during high temperature processing steps.
Among the objects of the present are the provision of a manufacturing process which produces ultra-flat semiconductor wafers ; the provision of a manufacturing process which produces semiconductor wafers having an enhanced gettering layer on the back surface; the provision of a manufacturing process which utilizes double side polishing in combination with a protective layer such as a low temperature oxide to produce an ultra-flat semiconductor wafer with enhanced back surface gettering; and the provision of a manufacturing process which produces low cost grade 1 semiconductor wafers with enhanced external gettering on the back surface.
Briefly, therefore, the present invention is directed to a process for manufacturing a semiconductor wafer sliced from a single crystal ingot. The process comprises a first double side polishing operation to increase wafer flatness and reduce damage on the wafer surfaces followed by forming a gettering layer on the back surface of the wafer. A protective layer is then formed on top of the gettering layer to protect the gettering layer during subsequent manufacturing and a second double side polishing operation is performed on the wafer to increase flatness. Finally, the protective layer is removed from the back surface of the semiconductor wafer.
The present invention is further directed to a process for manufacturing a semiconductor wafer sliced from a single crystal ingot. The process comprises first slicing a semiconductor wafer from a single-crystal ingot followed by lapping and/or grinding the wafer and etching the wafer in a chemical etchant. Next, a first double side polishing operation is performed on the wafer before a polycrystalline silicon layer is grown on the back surface to allow the back surface to getter impurities. Next, a silicon oxide layer is grown on top of the polycrystalline layer to protect the polycrystalline layer during further processing. Finally, a second double side polishing operation is performed on the wafer and the protective layer is removed prior to a final polishing operation.
The present invention is further directed to a semiconductor wafer having a front surface and a back surface wherein the back surface has an enhanced gettering layer. The wafer has a TTV of between about 0.1 micrometers and about 1 micrometer, an STIR between about 0.1 micrometers and about 0.2 micrometers and an average front surface roughness of about 5 nanometers over an area of about 1 millimeter by about 1 millimeter.
Other objects and features of this invention will be in part apparent and in part pointed out hereinafter.